Frequency synthesizers having phase lock loops (PLL) are widely utilized in electronic systems. Particularly, in communication systems frequency synthesizers provide an advantage in reducing the circuitry required to transmit and receive signals on different frequencies. Such digital phase lock loops are well known in the art. Digital PLLs may be used for generating a number of frequencies from a reference frequency, by simply changing a dividing factor.
A significant parameter when considering a synthesizer system is its lock time. The lock time is the amount of time elapsed before the PLL reaches steady state after being switched from one frequency to another frequency. A PLL having a wider loop bandwidth generally provides faster lock time. The frequency resolution of the PLL is another important parameter to consider, and is determined by the reference frequency in systems having an integer divider. For example a 5 KHz reference frequency provides a 5 KHz frequency resolution per divider step. If the reference frequency is increased, it is generally possible to increase the bandwidth of the phase lock loop. However, increasing the reference frequency produces a more coarse resolution for the PLL. In order to achieve finer resolution, fractional dividers can be used in the feedback of the loop. The fractional dividers, however, produce low frequency spurs, when dividing the output of a voltage controlled oscillator (VCO). Spurs appear as FM sidebands on the VCO output. These low frequency spurs may be reduced in the fractional divider itself. A frequency synthesizer with spur compensation is disclosed in my U.S. Pat. No. 4,816,774, the disclosure of which is hereby incorporated by reference. However, in order to mitigate the regeneration of these low frequency spurs, a phase detector having a linear transfer characteristics is necessary. Additionally, in some applications where fractional dividers are used, the narrow lock range of the PLL and the frequency range within which the PLL must operate makes frequency steering a necessity.
A digital phase detector comprises an integral part of a digital phase lock loop system. The digital phase detector provides an output, which is characterized by the phase difference between a first reference frequency signal and a second divided VCO signal. The use of dual state phase detectors or tri-state phase detectors in digital PLLs is well known.
A tri-state phase detector provides an output that has three conditions corresponding to a positive phase difference, a negative phase difference and a zero phase difference between the first and second input signals. The tri-state phase detector provides frequency steering. However, a tri-state phase detector does not provide the necessary linearity in the phase difference detecting range. Adaptive tri-state systems, where the output current is increased in the adapt mode to facilitate rapid frequency steering, are known.
A dual state phase detector provides an output having a duty cycle which is characterized by the phase difference between the first and second input signals. When the first and the second input signals are equal in frequency and 180 degrees out of phase, a 50% duty cycle at the output is provided. In practice the duty cycle of the output of the phase detector can be converted to a physical parameter such as current. Generally, a dual state phase detector acts linearly within a phase difference detecting range of 360 degrees. A major disadvantage of a dual state phase detector is its inability to steer the frequency in the correct direction. Accordingly, since the phase detector skips detection of a full cycle on one of the input signals, a "cycle skip" occurs. Therefor, it is desired to provide a linear phase detector having frequency steering capability.